High performance system-on-chip passive device using post passivation process

ABSTRACT

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

[0001] This application is a Continuation-In-Part of attorney docketMEG00-008CBBC, Ser. No. 10/303451, filing date Nov. 25, 2002, which is acontinuation of attorney docket MEG00-008CBB, Ser. No. 10/156590, filedon May 28, 2002, now issued as U.S. Pat. No. 6,489,647, which is aDivisional Application of MEG00-008CB, Ser. No. 09/970005, filing dateOct. 3, 2001, now U.S. Pat. No. 6,455,885, which is a DivisionalApplication of MEG00-008C, Ser. No. 09/721722, filing date Nov. 27,2000, now U.S. Pat. No. 6,303,423, which is a continuation-in-part ofattorney docket MEG00-008, Ser. No. 09/637926, filing date Aug. 14,2000, now abandoned, which is a continuation-in-part of attorney docketMSLIN98-002C, Ser. No. 09/251,183, filing date Feb. 17, 1999, now issuedas U.S. Pat. No. 6,383,916 B1, which is a continuation-in-part ofattorney docket MSLIN98-002, Ser. No. 09/216,791, filing date Dec. 21,1998, now abandoned, assigned to common assignee.

RELATED PATENT APPLICATIONS

[0002] This application is related to attorney docket number MEG02-016,Ser. No. ______, filed on ______, and assigned to a common assignee.

[0003] This application is related to attorney docket number MEG02-018,Ser. No. ______, filed on ______, and assigned to a common assignee.

BACKGROUND OF THE INVENTION

[0004] (1) Field of the Invention

[0005] The invention relates to the manufacturing of high performanceIntegrated Circuit (IC's), and, more specifically, to methods ofcreating high performance electrical components (such as an inductor) onthe surface of a semiconductor substrate by reducing the electromagneticlosses that are typically incurred in the surface of the substrate.

[0006] (2) Description of the Related Art

[0007] The continued emphasis in the semiconductor technology is tocreate improved performance semiconductor devices at competitive prices.This emphasis over the years has resulted in extreme miniaturization ofsemiconductor devices, made possible by continued advances ofsemiconductor processes and materials in combination with new andsophisticated device designs. Most of the semiconductor devices that areat this time being created are aimed at processing digital data. Thereare however also numerous semiconductor designs that are aimed atincorporating analog functions into devices that simultaneously processdigital and analog data, or devices that can be used for the processingof only analog data. One of the major challenges in the creation ofanalog processing circuitry (using digital processing procedures andequipment) is that a number of the components that are used for analogcircuitry are large in size and are therefore not readily integratedinto devices that typically have feature sizes that approach thesub-micron range. The main components that offer a challenge in thisrespect are capacitors and inductors, since both these components are,for typical analog processing circuits, of considerable size.

[0008] A typical application for inductors of the invention is in thefield of modern mobile communication applications. One of the mainapplications of semiconductor devices in the field of mobilecommunication is the creation of Radio Frequency (RF) amplifiers. RFamplifiers contain a number of standard components, a major component ofa typical RF amplifier is a tuned circuit that contains inductive andcapacitive components. Tuned circuits form, dependent on and determinedby the values of their inductive and capacitive components, an impedancethat is frequency dependent, enabling the tuned circuit to eitherpresent a high or a low impedance for signals of a certain frequency.The tuned circuit can therefore either reject or pass and furtheramplify components of an analog signal, based on the frequency of thatcomponent. The tuned circuit can in this manner be used as a filter tofilter out or remove signals of certain frequencies or to remove noisefrom a circuit configuration that is aimed at processing analog signals.The tuned circuit can also be used to form a high electrical impedanceby using the LC resonance of the circuit and to thereby counteract theeffects of parasitic capacitances that are part of a circuit. One of theproblems that is encountered when creating an inductor on the surface ofa semiconductor substrate is that the self-resonance that is caused bythe parasitic capacitance between the (spiral) inductor and theunderlying substrate will limit the use of the inductor at highfrequencies. As part of the design of such an inductor it is thereforeof importance to reduce the capacitive coupling between the createdinductor and the underlying substrate.

[0009] At high frequencies, the electromagnetic field that is generatedby the inductor induces eddy currents in the underlying siliconsubstrate. Since the silicon substrate is a resistive conductor, theeddy currents will consume electromagnetic energy resulting insignificant energy loss, resulting in a low Q inductor. This is one ofthe main reasons for a low Q value of a inductor, whereby the resonantfrequency of 1/{square root}(LC) limits the upper boundary of thefrequency. In addition, the eddy currents that are induced by theinductor will interfere with the performance of circuitry that is inclose physical proximity to the inductor. Furthermore, the fine metallines used to form the inductor also consume energy, due to the metal'sresistance, and result in low Q inductors.

[0010] It has already been pointed out that one of the key componentsused in creating high frequency analog semiconductor devices is theinductor that forms part of an LC resonance circuit. In view of the highdevice density that is typically encountered in semiconductor devicesand the subsequent intense use of the substrate surface area, thecreation of the inductor must incorporate the minimization of thesurface area that is required for the inductor, while at the same timemaintaining a high Q value for the inductor. Typically, inductors thatare created on the surface of a substrate are of a spiral shape wherebythe spiral is created in a plane that is parallel with the plane of thesurface of the substrate. Conventional methods that are used to createthe inductor on the surface of a substrate suffer several limitations.Most high Q inductors form part of a hybrid device configuration or ofMonolithic Microwave Integrated Circuits (MMIC's) or are created asdiscrete components, the creation of which is not readily integratableinto a typical process of Integrated Circuit manufacturing. It is clearthat, by combining the creation on one semiconductor monolithicsubstrate of circuitry that is aimed at the functions of analog datamanipulation and analog data storage with the functions of digital datamanipulation and digital data storage, a number of significantadvantages can be achieved. Such advantages include the reduction ofmanufacturing costs and the reduction of power consumption by thecombined functions. The spiral form of the inductor that is created onthe surface of a semiconductor substrate however results, due to thephysical size of the inductor, in parasitic capacitances between theinductor wiring and the underlying substrate and causes electromagneticenergy losses in the underlying resistive silicon substrate. Theseparasitic capacitances have a serious negative effect on thefunctionality of the created LC circuit by sharply reducing thefrequency of resonance of the tuned circuit of the application.

[0011] More seriously, the inductor-generated electromagnetic field willinduce eddy currents in the underlying resistive silicon substrate,causing a significant energy loss that results in low Q inductors.

[0012] The performance parameter of an inductor is typically indicatedis the Quality (Q) factor of the inductor. The quality factor Q of aninductor is defined as Q=Es/El, wherein Es is the energy that is storedin the reactive portion of the component while El is the energy that islost in the reactive portion of the component. The higher the quality ofthe component, the closer the resistive value of the componentapproaches zero while the Q factor of the component approaches infinity.For inductors that are created overlying a silicon substrate, theelectromagnetic energy that is created by the inductor will primarily belost in the resistive silicon of the underlying substrate and in themetal lines that are created to form the inductor. For components, thequality factor serves as a measure of the purity of the reactance (orthe susceptance) of the component, which can be degraded due to theresistive silicon substrate, the resistance of the metal lines anddielectric losses. In an actual configuration, there are always somephysical resistors that will dissipate power, thereby decreasing thepower that can be recovered. The quality factor Q is dimensionless. A Qvalue of greater than 100 is considered very high for discrete inductorsthat are mounted on the surface of Printed Circuit Boards. For inductorsthat form part of an integrated circuit, the Q value is typically in therange between about 3 and 10.

[0013] In creating an inductor on a monolithic substrate on whichadditional semiconductor devices are created, the parasitic capacitancesthat occur as part of this creation limit the upper bound of the cut-offfrequency that can be achieved for the inductor using conventionalsilicon processes. This limitation is, for many applications, notacceptable. Dependent on the frequency at which the LC circuit isdesigned to resonate, significantly larger values of quality factor,such as for instance 50 or more, must be available. Prior Art has inthis been limited to creating values of higher quality factors asseparate units, and in integrating these separate units with thesurrounding device functions. This negates the advantages that can beobtained when using the monolithic construction of creating both theinductor and the surrounding devices on one and the same semiconductorsubstrate. The non-monolithic approach also has the disadvantage thatadditional wiring is required to interconnect the sub-components of theassembly, thereby again introducing additional parasitic capacitancesand resistive losses over the interconnecting wiring network. For manyof the applications of a RF amplifier, such as portable battery poweredapplications, power consumption is at a premium and must therefore be aslow as possible. By raising the power consumption, the effects ofparasitic capacitances and resistive power loss can be partiallycompensated, but there are limitations to even this approach. Theseproblems take on even greater urgency with the rapid expansion ofwireless applications, such as portable telephones and the like.Wireless communication is a rapidly expanding market, where theintegration of RF integrated circuits is one of the most importantchallenges. One of the approaches is to significantly increase thefrequency of operation to for instance the range of 10 to 100 GHz. Forsuch high frequencies, the value of the quality factor obtained fromsilicon-based inductors is significantly degraded. For applications inthis frequency range, monolithic inductors have been researched usingother than silicon as the base for the creation of the inductors. Suchmonolithic inductors have for instance been created using sapphire orGaAs as a base. These inductors have considerably lower substrate lossesthan their silicon counterparts (no eddy current, hence no loss ofelectromagnetic energy) and therefore provide much higher Q inductors.Furthermore, they have lower parasitic capacitance and therefore providehigher frequency operation capabilities. Where however more complexapplications are required, the need still exists to create inductorsusing silicon as a substrate. For those applications, the approach ofusing a base material other than silicon has proven to be too cumbersomewhile for instance GaAs as a medium for the creation of semiconductordevices is as yet a technical challenge that needs to be addressed. Itis known that GaAs is a semi-insulating material at high frequencies,reducing the electromagnetic losses that are incurred in the surface ofthe GaAs substrate, thereby increasing the Q value of the inductorcreated on the GaAs surface. GaAs RF chips however are expensive, aprocess that can avoid the use of GaAs RF chips therefore offers thebenefit of cost advantage.

[0014] A number of different approaches have been used to incorporateinductors into a semiconductor environment without sacrificing deviceperformance due to substrate losses. One of these approaches has been toselectively remove (by etching) the silicon underneath the inductor(using methods of micro machining), thereby removing substrate resistiveenergy losses and parasitic effects. Another method has been to usemultiple layers of metal (such as aluminum) interconnects or of copperdamascene interconnects.

[0015] Other approaches have used a high resistivity silicon substratethereby reducing resistive losses in the silicon substrate. Resistivesubstrate losses in the surface of the underlying substrate form adominant factor in determining the Q value of silicon inductors.Further, biased wells have been proposed underneath a spiral conductor,this again aimed at reducing inductive losses in the surface of thesubstrate. A more complex approach has been to create an activeinductive component that simulates the electrical properties of aninductor as it is applied in active circuitry. This latter approachhowever results in high power consumption by the simulated inductor andin noise performance that is unacceptable for low power, high frequencyapplications. All of these approaches have as common objectives toenhance the quality (Q) value of the inductor and to reduce the surfacearea that is required for the creation of the inductor. The mostimportant consideration in this respect is the electromagnetic energylosses due to the electromagnetic induced eddy currents in the siliconsubstrate.

[0016] When the dimensions of Integrated Circuits are scaled down, thecost per die is decreased while some aspects of performance areimproved. The metal connections which connect the Integrated Circuit toother circuit or system components become of relative more importanceand have, with the further miniaturization of the IC, an increasinglynegative impact on circuit performance. The parasitic capacitance andresistance of the metal interconnections increase, which degrades thechip performance significantly. Of most concern in this respect is thevoltage drop along the power and ground buses and the RC delay of thecritical signal paths. Attempts to reduce the resistance by using widermetal lines result in higher capacitance of these wires.

[0017] Current techniques for building an inductor on the surface of asemiconductor substrate use fine-line techniques whereby the inductor iscreated under a layer of passivation. This however implies closephysical proximity between the created inductor and the surface of thesubstrate over which the inductor has been created (typically less than10 μm), resulting in high electro-magnetic losses in the siliconsubstrate which in turn results in reducing the Q value of the inductor.

[0018] U.S. Pat. No. 5,212,403(Nakanishi) shows a method of formingwiring connections both inside and outside (in a wiring substrate overthe chip) for a logic circuit depending on the length of the wireconnections.

[0019] U.S. Pat. No. 5,501,006(Gehman, Jr. et a].) shows a structurewith an insulating layer between the integrated circuit (IC) and thewiring substrate. A distribution lead connects the bonding pads of theIC to the bonding pads of the substrate.

[0020] U.S. Pat. No. 5,055,907(Jacobs) discloses an extended integrationsemiconductor structure that allows manufacturers to integrate circuitrybeyond the chip boundaries by forming a thin film multi-layer wiringdecal on the support substrate and over the chip. However, thisreference differs from the invention.

[0021] U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layerinterconnect structure of alternating polyimide (dielectric) and metallayers over an IC in a TAB structure.

[0022] U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method forreducing RC delay by a PBGA that separates multiple metal layers.

[0023] U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substratethat reduces RC delay by separating the power and I/O traces.

[0024] U.S. Pat. No. 6,008,102 (Alford et al.) shows a helix inductorusing two metal layers connected by vias.

[0025] U.S. Pat. No. 5,372,967 (Sundaram et al.) discloses a helixinductor.

[0026] U.S. Pat. No. 5,576,680 (Ling) and U.S. Pat. No. 5,884,990(Burghartz et al.) show other helix inductor designs.

SUMMARY OF THE INVENTION

[0027] It is the primary objective of the invention to improve the RFperformance of High Performance Integrated Circuits.

[0028] Another objective of the invention is to provide a method for thecreation of a high-Q inductor.

[0029] Another objective of the invention is to replace the GaAs chipwith a silicon chip as a base on which a high-Q inductor is created.

[0030] Yet another objective of the invention is to extend the frequencyrange of the inductor that is created on the surface of a siliconsubstrate.

[0031] It is yet another objective of the invention to create highquality passive electrical components overlying the surface of a siliconsubstrate.

[0032] The above referenced U.S. Pat. No. 6,383,916 adds, in a postpassivation processing sequence, a thick layer of dielectric over alayer of passivation and layers of wide and thick metal lines on top ofthe thick layer of dielectric. The present invention extends referencedU.S. Pat. No. 6,383,916 by in addition creating high quality electricalcomponents, such as an inductor, a capacitor or a resistor, on a layerof passivation or on the surface of a thick layer of dielectric. Inaddition, the process of the invention provides a method for mountingdiscrete passive electrical components on the surface of IntegratedCircuit chips.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a cross sectional representation of the interconnectionscheme shown in U.S. Pat. No. 6,383,916.

[0034]FIG. 2 is a cross sectional representation of an inductor of theinvention, created on a thick layer of polyimide.

[0035]FIG. 3 is a top view of an inductor created following the processof the invention.

[0036]FIG. 4 is a cross sectional representation of a substrate andoverlying layers, an inductor has been created on the surface of a thicklayer of polyimide, a layer of conductive material has been added tofurther insulate the inductor from the underlying silicon substrate.

[0037]FIG. 5a shows an inductor of the invention above a layer ofpassivation.

[0038]FIGS. 5b-5 c are a cross-sectional representation, and top view,respectively, of inductors of the invention formed on an isolatedsection of polymer.

[0039]FIG. 6a is a cross sectional representation of a transformeraccording to the invention, formed over a polymer layer, over a layer ofpassivation.

[0040]FIG. 6b is a cross sectional representation of a transformeraccording to the invention, with the bottom coil formed on a layer ofpassivation.

[0041]FIG. 6c is a three dimensional view of another embodiment of asolenoidal inductor of the invention, over a passivation layer.

[0042]FIG. 6d is a three-dimensional view of a solenoidal inductor ofthe invention, formed over a polymer layer, over a passivation layer.

[0043]FIG. 6e is a top view of the inductors of FIGS. 6c and 6 d.

[0044]FIG. 6f is a cross sectional representation of the structure ofFIG. 6e, taken along the line 6 f-6 f′ of FIG. 6e.

[0045]FIG. 6g is a three dimensional view of an inductor of theinvention, in the shape of a toroid.

[0046]FIG. 6h is a top view of the toroidal inductor of FIG. 6g.

[0047]FIGS. 7a-7 c is a cross sectional representation of a capacitor ofthe invention, formed over a polymer layer over passivation.

[0048]FIG. 8 is a cross sectional representation of a resistor of theinvention, formed over a passivation layer.

[0049]FIGS. 9a-9 b are cross sectional representations of a resistor ofthe invention, formed over a thick polymer layer, over a passivationlayer.

[0050]FIG. 10 is a cross sectional representation of, a siliconsubstrate over which a discrete electrical component has been mounted,on the top of a thick polymer layer, using surface mount technology.

[0051]FIG. 11 is a cross sectional representation of a siliconsubstrate, having a passivation layer on the surface of which a discreteelectrical component has been mounted, using surface mount technology.

[0052] FIGS. 12-18 depict, in cross-sectional form, the creation of goldmetal structures of the invention, through a layer of polymer.

[0053] FIGS. 19-23 depict the creation of copper metal structures of theinvention, through a layer of polymer.

[0054]FIGS. 24a-24 c show alternate methods of connecting to theinductor of the invention.

[0055]FIGS. 25 and 26 show extended methods of connecting a capacitorand a resistor under the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] U.S. Pat. No. 6,383,916, assigned to a common assignee as thecurrent invention, teaches an Integrated Circuit structure wherere-distribution and interconnect metal layers are created in layers ofdielectric over the passivation layer of a conventional IntegratedCircuit (IC). A layer of passivation is deposited over the IC, a thicklayer of polymer is alternately deposited over the surface of the layerof passivation, and thick, wide metal lines are formed over thepassivation.

[0057] U.S. Pat. No. 6,303,423, also assigned to a common assignee asthe current invention, addresses, among other objectives, the creationof an inductor whereby the emphasis is on creating an inductor of high Qvalue above the passivation layer of a semiconductor substrate. The highquality of the inductor of the invention allows for the use of thisinductor in high frequency applications while incurring minimum loss ofpower. The invention further addresses the creation of a capacitor and aresistor on the surface of a silicon substrate whereby the mainobjective (of the process of creating a capacitor and resistor) is toreduce parasitics that are typically incurred by these components in theunderlying silicon substrate.

[0058] Referring now more specifically to FIG. 1, there is shown a crosssection of one implementation of U.S. Pat. No. 6,383,916. The surface ofsilicon substrate 10 has been provided with transistors 11 and otherdevices (not shown in FIG. 1). The surface of substrate 10 is covered bya interlevel dielectric (ILD) layer 12, formed over the devices.

[0059] Layers 14 represent metal and dielectric layers that aretypically created over ILD 12. Layers 14 contain one or more layers ofdielectric, interspersed with one or more metal interconnect lines 13that make up a network of electrical connections. At a top metal layerare points 16 of electrical contact. These points 16 of electricalcontact can establish electrical interconnects to the transistors andother devices 11 that have been provided in and on the surface of thesubstrate 10. A passivation layer 18, formed of, for example, acomposite layer of silicon oxide and silicon nitride, is deposited overthe surface of layers 14, and function to prevent the penetration ofmobile ions (such as sodium ions), moisture, transition metal (such asgold, copper, silver), and other contamination. The passivation layer isused to protect the underlying devices (such as transistors, polysiliconresistors, poly-to-poly capacitors, etc.) and the fine-line metalinterconnection.

[0060] The key steps of U.S. Pat. No. 6,383,916, begin with thedeposition of a thick layer 20 of polyimide that is deposited over thesurface of passivation layer 18. Access must be provided to points ofelectrical contact 16, for this reason a pattern of openings 22, 36 and38 is formed through the polyimide layer 20 and the passivation layer18, the pattern of openings 22, 36 and 38 aligns with the pattern ofelectrical contact points 16. Contact points 16 are, by means of theopenings 22/36/38 that are created in the layer 20 of polyimide,electrically extended to the surface of layer 20.

[0061] Layer 20 is a polymer, and is preferably polyimide. Polymer 20may optionally be photosensitive. Examples of other polymers that can beused include benzocyclobutene (BCB), parylene or epoxy-based materialsuch as photoepoxy SU-8 (available from Sotec Microsystems, Renens,Switzerland).

[0062] After formation of openings 22/36/38, metallization is performedto create patterned wide metal layers 26 and 28, and to connect tocontact points 16. Lines 26 and 28 can be of any design in width andthickness to accommodate specific circuit design requirements, which canbe used for power distribution, or as a ground or signal bus.Furthermore, metal 26 may be connected off-chip through wire bonds orsolder bumps.

[0063] Contact points 16 are located on top of a thin dielectric (layers14, FIG. 1), and the pad size must be kept small to minimize capacitancewith underlying metal layers. In addition, a large pad size willinterfere with the routing capability of the layer of metal.

[0064] Layer 20 is a thick polymer dielectric layer (for example,polyimide) having a thickness in excess of 2 μm (after curing). Therange of the polymer thickness can vary from 2 μm to 150 μm, dependenton electrical design requirements. For a thicker layer of polyimide, thepolyimide film can be multiple coated and cured.

[0065] U.S. Pat. No. 6,383,916 B1 allows for the interconnection ofcircuit elements at various distances, over the path 30/32/34 shown inFIG. 1, using the thick, wide (as compared to the underlying “fine line”metallization in layers 14) metal of 28. Thick, wide metal 28 hassmaller resistance and capacitance than the fine line metal 14 and isalso easier and more cost effective to manufacture.

[0066]FIG. 2 shows how the interconnect aspect of U.S. Pat. No.6,383,916, can be modified to form an inductor on the surface of thethick layer 20 of polyimide. The inductor is created in a plane that isparallel with the surface of the substrate 10 whereby this plane howeveris separated from the surface of the substrate 10 by the combinedheights of layers 12, 14, 18, and 20. FIG. 2 shows a cross section 40 ofthe inductor taken in a plane that is perpendicular to the surface ofsubstrate 10. The wide and thick metal will also contribute to areduction of the resistive energy losses. Furthermore, the lowresistivity metal, such as gold, silver and copper, can be applied usingelectroplating, the thickness can be about 20 μm.

[0067] By increasing the distance between the inductor and thesemiconductor surface, as compared to prior art approaches in which theinductor is formed under the passivation, the electromagnetic field inthe silicon substrate will be reduced as the distance is increased, andthe Q value of the inductor can be increased. The inductor overlies thelayer of passivation and by, in addition, creating the inductor on thesurface of a thick layer of dielectric (such as a polymer) formed overthe passivation layer. In addition, by using wide and thick metal forthe creation of the inductor, the parasitic resistance is reduced.

[0068] In an important feature of the invention, the openings 19 inpassivation layer 18 may be as small as 0.1 μm wide. Thus, contact pads16 may also be nearly as small, which allows for greater routingcapability in the top fine-line metallization layer, and lowercapacitance.

[0069] In another important feature of the invention, the openings22/36/38 in polymer 20 are larger than the passivation openings 19. Thepolymer openings 22/36/38 are aligned with passivation openings 19. Thelarger polymer openings allow for relaxed design rules, simpler openingformation, and the use of a thick metal layer for the post-passivationmetallization of the invention.

[0070]FIG. 2 illustrates interconnect structure 26 as well as inductor40, wherein the inductor includes two contacts 41 and 43, throughpolymer layer 20 to contact pads 16.

[0071] In another feature of the invention, the FIG. 2 structure may becovered by an additional layer of polymer (not shown).

[0072]FIGS. 24a and 24 b illustrate another feature of the invention, inwhich contacts to the inductor are formed in a different manner than the2 downward contacts of FIG. 2. Specifically, in FIG. 24a, a layer 35 ofdielectric, preferably polyimide or the like, is deposited overinterconnection 26 and inductor 40. An opening 36′ to one end of theinductor is then formed to expose one terminal of the inductor 40.Inductor 40 in FIG. 24a thus can have one contact extending upward, anda second contact 40′ extending downward, in a “one-up, one-down”configuration.

[0073]FIG. 24b illustrates another alternative, in which 2 upwardcontact openings 36′ and 38′ are formed from inductor 40, in a “two-up”configuration.

[0074] In both FIGS. 24a and 24 b, the upward contacts may be used forconnection to external devices or packaging, by way of wire bonding,solder bumps, or the like. For wire bonding, an upper surface ofinductor 40 must be formed of a wire-bondable material such as Au or Al.For solder bump connection, under bump metallization (UBM) would beformed in the upward contact opening, followed by solder bump formation.

[0075] In either of the FIG. 24a or 24 b configurations,interconnections to other contact pads on the same die (as opposed toconnections to external devices, as described in the previous paragraph)may be made through openings 36′ and/or 38′, using similar metallization(but as an additional layer) as used for structure 26 and inductor 40.

[0076] Referring now to FIG. 24c, another feature of the invention isshown in which extension 89, connected to inductor 40, is used torelocate an inductor contact opening 36″ to another location on the die,such as at the die edge. This may be useful for ease of wire bonding,for example. Opening 38″ is formed as earlier described. Extension 89 isformed at the same time and of the same metallization as structure 26and inductor 40.

[0077] Similarly, extension 89 could be used to interconnect inductor 40to another contact point on the same die, by making a downward contact(not shown, but described earlier) instead of upward contact 36″.

[0078] If a contact to a center point of the inductor, such as thatshown under opening 38″ in FIG. 24c, is desired, then such contactcannot of course be made by an extension such as 40′, but instead mustbe either upward or downward.

[0079]FIG. 3 shows a top view 42 of the spiral structure of the inductor40 that has been created on the surface of layer 20 of dielectric. Theinductor 40 cross section that is shown in FIG. 2 is taken along line2-2 of FIG. 3.

[0080]FIG. 4 shows a cross section of inductor 40 whereby the inductorhas been further isolated from the surface of the substrate 10 by theaddition of a conductive plate 44′, of conducting material, formed undersubstantially all of the inductor, and preferably formed of Cu (copper)or Au (gold). The surface area of the conductive plate 44′ typicallyextends over the surface of passivation layer 18 such that the inductor40 aligns with and overlays the conductive plate 44′, the surface areaof conductive plate 44′ can be extended slightly beyond these boundariesto further improve shielding the surface of substrate 10 from theelectromagnetic field of inductor 40.

[0081] Conductive plate 44′ can be connected to one of the inductorterminals (as shown in FIG. 4, in which it is connected to the rightmostinductor terminal 43), or may be left at a floating voltage level, ormay be connected to another voltage level, deciding on the system'selectrical design.

[0082] Conductive plate 44′ is formed using the methods and material ofthe invention, as later described with regard to the metal layer used toform metal interconnect 26 and inductor 40. Conductive plate 44′ isformed at the same time as connectors 44, which serve to connect thenext level metal to contact points 16, as shown in FIG. 4.

[0083] Optionally, a second polymer layer 47 may be deposited overinductor 40 and interconnect structure 26, to provide additionalprotection of the metal structures.

[0084] Referring now to FIGS. 12-23, further details are provided forforming the post passivation inductor (and other passive devices) of theinvention. In FIG. 12, a substrate 80 is shown, which could be anunderlying dielectric layer, and a metal contact point 81, preferablycomprising aluminum. A layer 84 of passivation has been patternedcreating an opening 82 through layer 84 that exposes the contact pad 81.Layer 86 is a layer of polymer, preferably polyimide, as earlierdescribed, deposited over the layer 84 of passivation, including theexposed surface of the contact pad. Polymer layer 86, such as polyimide,is typically spun on. For some thick layers of polymer, the polymer canbe screen printed. Alternately, a laminated dry film polymer may beused.

[0085]FIG. 13 illustrates forming an opening 87 in polymer 86, whereinthe polymer opening 87 is larger than passivation opening 82. Opening 87is depicted having sloped sides 85. Polymer layer 86 is exposed anddeveloped to form opening 87, which initially has vertical sidewalls.However, the subsequent curing process causes the sidewalls to have aslope 85, and a opening 87 to have a resultant partially conical shape.The sidewall slope 85 may have an angle of 45 degrees or more, and istypically between about 50 and 60 degrees. It may be possible to formthe sidewalls with an angle as small as 20 degrees.

[0086] By creating relatively large vias through the layer of polyimideor polymer, aligned with smaller vias created through the underlyinglayer of passivation, aligned with underlying sub-micron metal layer, itis clear that the sub-micron metal vias can effectively be enlarged whenprogressing from the sub-micron metal layer to the level of the widemetal.

[0087] Continuing to refer to FIG. 13, one metallization system andprocess for forming the post passivation interconnect and inductor ofthe invention is depicted. First, a glue/barrier layer 88, preferablycomprising TiW, is deposited, preferably by sputtering to a thickness ofbetween about 500 and 5,000 Angstroms. A gold seed layer 90, is nextsputter deposited over the glue/barrier 88, to a thickness of betweenabout 300 and 3,000 Angstroms.

[0088] Referring now to FIG. 14, a bulk layer 92 of gold (Au) is nextformed by electroplating, to a thickness of between about 1 and 20 μm.Electroplating is preceded by deposition of a thick photoresist 94 (to athickness greater than the desired bulk metal thickness), andconventional lithography to expose the gold seed layer 90 in those areaswhere electroplating thick metallization is desired.

[0089] After electroplating, photoresist 94 is removed, as shown in FIG.15. Glue/barrier Layer 88 and gold seed layer 90 are now removed, asshown in FIG. 16, by etching, using bulk Au layer 92 as a mask. One coilof inductor 40 is shown, but it would be understood that the completeinductor would be formed at the same time.

[0090] In another feature of the invention, polymer opening 87 may beonly partially filled, as shown in FIGS. 17-18, which provides tightdesign rules for fine-pitch inductors. The design rule of polymeropening 87 is typically about 15 μm, while the metal traces of inductorare as tight as a 4 μm pitch. Therefore, patterning metal inside thepolyimide opening is a very important feature of this technology.

[0091] Glue/barrier layer 88 and Au seed layer 90 are sputtered aspreviously described, and photoresist 95 formed as shown in FIG. 17,followed by electroplating gold bulk layer 92. Photoresist 95 is thenstripped, and the seed layer and glue/barrier etched as previouslydescribed, and as shown in FIG. 18.

[0092] In another embodiment of the invention, copper may be used as thebulk metal in the post-passivation metallization scheme. The FIG. 13structure is a starting point. Next, as shown in FIG. 19, a glue/barrierlayer 100 of Cr or Ti is sputter deposited to a thickness of betweenabout 200 and 2000 Angstroms. Next, a Cu seed layer 102 is sputterdeposited to a thickness of between about 2,000 and 10,000 Angstroms.Bulk layer 104 of Cu is next electroplated to a thickness of betweenabout 3 and 20 μm, also using a photoresist 94′ and conventionallithography to define the areas to be electroplated. Finally, anoptional cap layer 106 comprising Ni may also be formed, also byelectroplating, to a thickness of between about 0.1 and 3 μm.

[0093] Referring to FIG. 20, photoresist 94′ is stripped, exposing Cuseed layer 104. Glue/barrier layer 100 and Cu seed layer 102 are nowremoved, as shown in FIG. 21, by etching. The bulk Cu layer 104 is usedas a mask for this etch.

[0094] If optional Ni cap layer 106 is used, it acts as an etch stopduring the etching of glue/barrier 100 and seed layer 102. With the Nicap, a faster Cu etch recipe can be used for removing the seed layersince there is no loss of Cu bulk in this configuration.

[0095] One coil of inductor 40 is shown, but it would be understood thatthe complete inductor would be formed at the same time.

[0096] In another feature of the invention and as earlier described,polymer opening 87 may be only partially filled, as shown in FIGS.22-23. Glue/barrier layer 100 and Cu seed layer 102 are sputtered aspreviously described, and photoresist 95′ formed as shown in FIG. 22,followed by electroplating Cu bulk layer 104 and Ni 106. Photoresist 95′is then stripped, and the seed layer and glue/barrier etched aspreviously described, and as shown in FIG. 23.

[0097] Referring now to FIG. 5a, layers similar to earlier descriptionsare shown whereby in this case no layer of polyimide has been depositedover the layer of passivation. An inductor 19 has been created on thesurface of layer 18 of passivation. The ohmic resistivity of the metalthat is used for inductor 19 must be as low as possible. For thisreason, the use of a thick layer of, for instance, gold is preferred forthe formation of inductor 19. It has been shown that a thick layer ofgold increased the Q value of inductor 19 from about 5 to about 20 for2.4 GHz applications.

[0098] The FIG. 5a inductor may be connected to other elements invarious configurations, as earlier described. These include bothterminals being connected to lower levels, as shown in FIG. 4, one upand one down as shown in FIG. 24a, or both up as in FIG. 24b.

[0099] An additional layer of polymer (not shown) may optionally beformed over inductor 19.

[0100] In another feature of the invention, polymer islands may beformed only under the inductor coils, and not elsewhere over thepassivation layer, in order to reduce the stress caused by a largersheet of polymer. This is depicted in FIGS. 5b-5 c, which are across-sectional representation, and top view, respectively, of inductorsof the invention formed on polymer islands. Each island may contain oneor more than one inductor, such as on the right-most island of FIG. 5chaving a first inductor 40′ and second inductor 40′″.

[0101] Referring first to FIG. 5b, isolated islands of polymer 20′ areformed, by depositing a polymer layer and then patterning the polymerlayer to form the polymer islands. The polymer islands may also beformed by screen printing, or by dry film lamination. The islands ofpolymer 20′ are formed only at the location of inductors 40′ and 40″,which are formed subsequent to polymer island formation.

[0102] The inductors 40′ and 40″ of FIG. 5b are formed as earlierdescribed. For illustrative purposes, inductor 40″ is shown withdownward contacts 41′ and 43′ connecting to metal contact points 16.Inductors 40′ are shown without contacts but could be connected upwardfor connection to external circuits, as described elsewhere.

[0103]FIG. 5c is a top view of the inductors of the invention shown inFIG. 5b, in which the FIG. 5b cross-section is taken along line 5 b-5 bin FIG. 5c. It can be seen in FIG. 5c that polymer islands 20′ areisolated from one another, and polymer is only located under inductorlocations—passivation layer 18 is exposed in all other areas of thesubstrate.

[0104] An additional protective layer of polymer (not shown) mayoptionally be formed over inductors 40′ and 40″.

[0105] In a similar fashion to that shown in FIGS. 5b-5 c for inductors,polymer islands may be formed under other devices of the invention,including passive devices such as resistors and capacitors.

[0106]FIGS. 6a-6 b depict a transformer made according to the invention.The transformer consists of bottom coil 60, and top coil 62, isolated bya dielectric layer 47. Polymer layers 20, 47 and 64 are formed, andcomprise materials, previously described. Openings 66 are provided intop polymer layer 64 for connections to the top coil 62.

[0107]FIG. 6b is a cross-sectional representation of a transformer ofthe invention, in which the bottom coil 60 is formed directly onpassivation layer 18.

[0108]FIG. 6c is a three-dimensional view of a solenoid structure of aninductor 19 that has been created on passivation layer 18, according tothe invention. Further highlighted in FIG. 6c are:

[0109]23, vias that are created in the thick layer of polymer 20, havingsubstantially vertical metal segments

[0110]25, the bottom metal segments of the solenoid

[0111]27, the top metal segments of the solenoid.

[0112] The top and bottom metal segments 25, 27 are connected, as shown,by the substantially vertical metal segments formed in vias 23, to forma continuous solenoid.

[0113]FIG. 6d is a three dimensional view of a solenoid that has beencreated on a first layer 29 of polymer, having vias 23 created in asecond layer of polymer.

[0114]FIG. 6e is a top view of the solenoid of FIGS. 6c and 6 d. Vias 23are shown, connecting top metal segments 27 to bottom metal segments 25.

[0115]FIG. 6f is a cross section of the structure of FIGS. 6c-e, takenalong line 6 f-6 f′ of FIG. 6e.

[0116] Referring now to FIGS. 6g-6 h, a toroidal inductor 68 is shown,also formed according to the method and structure of the invention. InFIG. 6g, a three-dimensional view is shown, including top metal wires27′, with vias 23′ connecting the top metal wires to the bottom metalwires 25′.

[0117]FIG. 6h shows, for further clarification, a top view of thetoroidal inductor 68 of FIG. 6g. The highlighted features of this figurehave previously been explained and therefore do not need to be furtherdiscussed at this time.

[0118] Besides inductors, it is very useful to form other passivedevices, such as capacitors and resistors, using the method andstructure of the invention.

[0119]FIG. 7a is a cross section of a capacitor that has been createdover a substrate 10. A layer (or layers) 14 of conductive interconnectlines and contact points 16 have been created over substrate 10. A layer18 of passivation has been deposited over layer 14, with openingscreated in layer 18 of passivation through which contact pads 16 can beaccessed.

[0120] A capacitor contains, as is well known, a lower plate, an upperplate and a layer of dielectric that separates the upper plate from thelower plate. FIG. 7a includes lower plate 42, upper plate 45, anddielectric layer 46. The upper and lower plates are formed as earlierdescribed, using electroplated Au or Cu for the bulk metals. An optionalprotective polymer, preferably polyimide, may be formed over thecapacitor. Contacts to the capacitor may be made as described earlierfor inductor terminals (both down, one up and one down, or both up).

[0121] Lower plate 42 is formed to a thickness of between about 0.5 and20 μm. Layer 46 of dielectric is between about 500 and 50,000 Angstroms.Upper plate 45 is between about 0.5 and 20 μm thick.

[0122] The post-passivation capacitor shown in cross section in FIG. 7ahas:

[0123] reduced parasitic capacitance between the capacitor and theunderlying silicon substrate

[0124] allowed for the use of a thick layer of conductive material forthe capacitor plates, reducing the resistance of the capacitor; this isparticularly important for wireless applications

[0125] can use high-dielectric-constant material such as TiO₂ or Ta₂O₅,in addition to polymer, Si₃N₄ or SiO₂, for the dielectric between theupper and the lower plate of the capacitor, resulting in a highercapacitive value of the capacitor.

[0126] The capacitor of FIG. 7a may alternately be formed above apolymer layer (deposited over passivation 18), similar to the inductorof FIG. 4.

[0127] Dielectric layer 46 is formed of a high-K dielectric materialsuch as Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON, which are typicallydeposited by CVD (Chemical Vapor Deposition).

[0128] Alternately, the dielectric layer 46 can be a polymer film,including polyimide, benzocyclobutene (BCB), parylene or an epoxy-basedmaterial such as photoepoxy SU-8.

[0129]FIGS. 7b-7 c show a cross section where, as in FIG. 7a, acapacitor is created. In the cross section that is shown in FIG. 7b athick layer 20 of polymer has been deposited over the surface of thepassivation layer 18 and has been patterned in order to make the contactpads 16 accessible though the thick layer 20 of polymer. FIG. 7b showsthe polymer vias having a smaller via diameter than the vias createdthrough the layer of passivation. It is however preferred, as shown inFIG. 7c, that larger vias be used in conjunction with smallerpassivation vias. The thick layer 20 of polymer moves most of thecapacitor, that is the lower plate 42, the upper plate 45 and thedielectric 46, further from the surface of substrate 10 by a distanceequal to the thickness of layer 20. It has previously been stated thatthe range of polyimide thickness can vary from 2 μm to 150 μm, dependingon electrical design requirements. This leads to a significant increasein distance between the capacitor and underlying structures, includingmetal lines and/or the silicon substrate, so that parasitic capacitanceis significantly reduced.

[0130]FIGS. 7a-7 c depict both capacitor terminals being connected downto a lower layer. The capacitor may also be contacted in one-up-one-downconfiguration—as shown in FIG. 25—or a two-up technique, as previouslydescribed with reference to FIG. 24b.

[0131] Specifically relating to the cross section of FIGS. 7a-7 c, theupper capacitor plate 45 can be connected in an upward manner through alayer of dielectric that has been deposited over the second capacitorplate 45 of FIGS. 7a-7 c. This is further highlighted in the crosssection of FIG. 25, wherein a layer 35 of dielectric has been depositedover the capacitor upper plate 45, with an opening 37 created throughthe layer 35 of dielectric to expose the capacitor upper plate 45, forfurther connection to external circuits.

[0132] The capacitor of FIGS. 7a-7 c may optionally be covered with aprotective layer of polymer, as previously described.

[0133]FIG. 8 shows a cross section of a substrate 10 over which has beendeposited a layer 18 of passivation, with a resistor 48 formed overpassivation layer 18. A resistor, as is well known, is created byconnecting two points with a material that offers electrical resistanceto the passage of current through the material. For the creation oflayer 48 a resistive material is used, such as TaN, NiCr, NiSn, tungsten(W), TiW, TiN, Cr, Ti, TaSi or Ni. Among these resistive materials, NiCrprovides the best TCR (Temperature Coefficient of Resistance), which canbe as small as 5 ppm/° C. Resistor dimensions such as thickness, lengthand width of deposition of high resistive material 48 are applicationdependent. The resistor that is shown in cross section in FIG. 8 is, asare the capacitors of FIGS. 7a-7 c, created in a post-passivationprocess on the surface of layer 18 of passivation.

[0134]FIGS. 9a-9 b shows the resistor of the invention formed over athick layer of polymer 20, connected to contact pads 16. By increasingthe distance between the body of the resistor and the substrate (by thethickness of the polymer layer 20 and other intervening layers) theparasitic capacitance between the body of the resistor and the substrateis reduced, resulting in an improved resistive component (reducedparasitic capacitive loss, improved high frequency performance).

[0135]FIGS. 8, 9a and 9 b show a “two-down” system for contacting theterminals of the resistor 48. The resistor may also be contacted inone-up-one-down configuration, as shown in FIG. 26, or a two-uptechnique, as previously described with reference to the inductor ofFIG. 24b.

[0136] An additional layer of polymer, to protect the resistor, mayoptionally be formed over the resistor of FIGS. 8, 9a and 9 b.

[0137] Further applications of the post-passivation processing of theinvention are shown in FIGS. 10 and 11, which concentrate on makingcontact points between contact pads 16 and an overlying electriccomponent, such as a discrete inductor, capacitor, resistor or otherpassive device. Interconnect metal 50 of the invention is formed inpolymer openings, as previously described, which are aligned withsmaller passivation openings, to connect to pads 16, and serves as anunder-bump metal (UBM). Solder contact bumps are formed over UBM 50using conventional methods of selective solder deposition (plating, ballmounting, or screen printing on the surface of contacts 50), theapplication of a flux on the deposited solder and flowing the solder. Adiscrete device 54 is connected to solder balls 52 and has solder 53 tofacilitate the connection. This is similar to the surface mounttechnology used in the assembly of printed circuit boards. The discreteelectrical component may be, but is not limited to, devices such asinductors, capacitors or resistors.

[0138]FIG. 11 illustrates mounting of discrete device 54, using solderbumps 56, and UBM 50, directly over passivation layer 18.

[0139] The discrete components of FIGS. 10 and 11 have the advantages ofperformance and cost savings since the discrete component does not haveto be mounted on a Printed Circuit Board as is the common practice inthe art.

[0140] UBM 50 is formed using the metallization scheme of the invention(as shown and described with respect to FIGS. 12-23), except that whenAu is used as the bulk layer, its thickness is in the range of betweenabout 0.1 and 20 μm, the thinner range being preferable to avoid a highgold concentration in the solder near the UBM/solder interface, afterprocessing.

[0141] The invention and its various features provide the advantages of:

[0142] the discrete components provide optimized parameters and can bemounted close to the circuits, which offer true system-on-chipperformance

[0143] the discrete components mounting close to the circuits alsominimizes parasitics

[0144] the post-passivation process of the invention allows for theselection of discrete component design parameters that result in reducedresistance of the discrete capacitor and the discrete inductor, this isfurther clear from the following comparison between prior art processesand the processes of the invention.

[0145] Prior approaches in the art uses thinner metal for inductors,requiring wider coils (to minimize resistance), resulting in increasedsurface area, increasing the parasitic capacitance of the inductor andcausing eddy current losses in the surface of the substrate.

[0146] The present invention by contrast, can use easily formed thickmetal layers, the thickness reducing resistance. Use of polymer 20further separates the components formed from underlying structures,reducing capacitance. With the reduced capacitance, a higher frequencyof operation results due to a higher resonant frequency.

[0147] Although the preferred embodiment of the present invention hasbeen illustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

What is claimed is:
 1. A post passivation system, comprising: asemiconductor substrate, having at least one interconnect metal layerover said semiconductor substrate, and a passivation layer over the atleast one interconnect metal layer, wherein the passivation layercomprises at least one passivation opening through which is exposed atleast one top level metal contact point; and a passive device, formedover said passivation layer and connected to said at least one top levelmetal contact point; wherein said passivation opening's width is largerthan about 0.1 um.
 2. The system of claim 1 further comprising a polymerlayer formed over said passivation layer and under said passive device.3. The system of claim 2 wherein said polymer layer has at least onepolymer opening, wherein said polymer opening is aligned with saidpassivation opening.
 4. The system of claim 3 wherein said polymeropening is larger than said passivation opening.
 5. The system of claim4, wherein said passive device is connected to one or more of said toplevel metal contact points through said polymer opening and saidpassivation opening.
 6. The system of claim 5, wherein metal used toform said passive device and to connect said passive device to said oneor more of said top level metal contact points completely coverssidewalls of said polymer opening.
 7. The system of claim 5, whereinmetal used to form said passive device and to connect said passivedevice to said one or more of said top level metal contact points onlypartially covers sidewalls of said polymer opening.
 8. The system ofclaim 2 wherein said polymer layer comprises polyimide, benzocyclobutene(BCB), parylene or an epoxy-based material.
 9. The system of claim 1,wherein said passive device is a capacitor.
 10. The system of claim 9further comprising metal interconnections, formed of a same material asconductive plates of said capacitor and formed over said passivationlayer, and connected to at least one of said top level metal contactpoints.
 11. The system of claim 10 wherein said metal interconnectionsand said conductive plates are formed of a bottom glue/barrier layer, aseed layer over said bottom glue/barrier layer, and a bulk layer oversaid seed layer.
 12. The system of claim 11 wherein said bottomglue/barrier layer is TiW, said seed layer is Au, and said bulk layer isAu.
 13. The system of claim 11 wherein said bottom glue/barrier layer isCr or Ti, said seed layer is Cu, and said bulk layer is Cu.
 14. Thesystem of claim 13 further comprising a cap layer of Ni formed over saidbulk layer of Cu.
 15. The system of claim 1 wherein said passive devicehas first and second terminals, said first and second terminals eachbeing connected downward to one of said top level metal contact points.16. The system of claim 15, wherein said passive device is a capacitor,said capacitor has bottom and top plates, with a dielectric layerbetween said bottom and top plates, wherein one of said first and secondterminals connected to one of said bottom and top plates, and whereinanother of said first and second terminals is connected to another ofsaid bottom and top plates.
 17. The system of claim 1 further comprisinga protective layer of polymer formed over said passive device and oversaid passivation layer.
 18. The system of claim 17 wherein said passivedevice has first and second terminals, said first terminal beingconnected to one of said top level metal contact points, and said secondterminal exposed through said protective layer of polymer.
 19. Thesystem of claim 18 further comprising a solder bump, solder ball, orwire bond pad connected to said second terminal.
 20. The system of claim18, wherein said passive device is a capacitor, said capacitor hasbottom and top plates, with a dielectric layer between said bottom andtop plates, one of said first and second terminals connected to one ofsaid bottom and top plates, and another of said first and secondterminals connected to another of said bottom and top plates.
 21. Thesystem of claim 9, wherein said capacitor is formed of bottom and topplates, with a dielectric layer between said bottom and top plates. 22.The system of claim 21, wherein said dielectric layer is Si₃N₄, TEOS,Ta₂O₅, TiO₂, SrTiO₃, or SiON.
 23. The system of claim 21, wherein saiddielectric layer is a polymer, and wherein said polymer is polyimide,benzocyclobutene (BCB), parylene or an epoxy-based material.
 24. Thesystem of claim 21 further comprising a first polymer layer formed oversaid passivation layer and under said capacitor.
 25. The system of claim24 wherein said first polymer layer has at least one first polymeropening, wherein said first polymer opening is aligned with saidpassivation opening.
 26. The system of claim 25 wherein said firstpolymer opening is larger than said passivation opening.
 27. The systemof claim 25 wherein said first polymer opening is smaller than saidpassivation opening.
 28. The system of claim 26 wherein said dielectriclayer has a dielectric layer opening aligning with said passivationopening, wherein said dielectric layer opening is larger than said firstpolymer opening.
 29. The system of claim 27 wherein said dielectriclayer has a second polymer opening aligning with said passivationopening, wherein said dielectric layer opening is smaller than saidfirst polymer opening.
 30. The system of claim 2, wherein said polymerlayer is formed only under passive device, to form polymer islands,thereby reducing stress in said polymer layer.
 31. The system of claim1, wherein said passive device is a resistor.
 32. The system of claim31, wherein said resistor is formed of TaN, NiCr, NiSn, tungsten (W),TiW, TiN, Cr, Ti, TaSi or Ni.
 33. The system of claim 32 furthercomprising metal interconnections, formed of a different material thansaid resistor, formed over said passivation layer, and connected to atleast one of said top level metal contact points.
 34. The system ofclaim 33 wherein said metal interconnections are formed of a bottomglue/barrier layer, a seed layer over said bottom glue/barrier layer,and a bulk layer over said seed layer.
 35. The system of claim 32wherein said bottom glue/barrier layer is TiW, said seed layer is Au,and said bulk layer is Au.
 36. The system of claim 33 wherein saidbottom glue/barrier layer is Cr or Ti, said seed layer is Cu, and saidbulk layer is Cu.
 37. The system of claim 36 wherein said resistor hasfirst and second terminals, said first and second terminals each beingconnected downward to one of said top level metal contact points. 38.The system of claim 31 further comprising a protective layer of polymerformed over said resistor and over said passivation layer.
 39. Thesystem of claim 38 wherein said resistor has first and second terminals,said first terminal being connected to one of said top level metalcontact points, and said second terminal exposed through said protectivelayer of polymer.
 40. The system of claim 37 further comprising a solderbump, solder ball, or wire bond pad connected to said second terminal.41. The system of claim 31 further comprising a first polymer layerformed over said passivation layer and under said resistor.
 42. Thesystem of claim 41 wherein said first polymer layer has at least onefirst polymer opening, wherein said first polymer opening is alignedwith said passivation opening.
 43. The system of claim 42 wherein saidfirst polymer opening is larger than said passivation opening.
 44. Thesystem of claim 43 wherein said first polymer opening is smaller thansaid passivation opening.
 45. The system of claim 41, wherein saidpolymer layer is formed only under said resistor, to form polymerislands, thereby reducing stress in said polymer layer.
 46. A postpassivation system, comprising: a semiconductor substrate, having atleast one interconnect metal layer over said semiconductor substrate,and a passivation layer over the at least one interconnect metal layer,wherein the passivation layer comprises at least one passivation openingthrough which is exposed at least one top level metal contact point; apassive device, formed over said passivation layer; metalinterconnections, formed of a same material as said passive device andformed over said passivation layer, and connected to at least one ofsaid top level metal contact points; wherein said passivation opening'swidth is larger than about 0.1 um.
 47. The system of claim 46 whereinsaid passive device is a capacitor.
 48. The system of claim 47 furthercomprising a protective layer of polymer formed over said capacitor andover said passivation layer.
 49. The system of claim 48 wherein saidcapacitor has first and second terminals, said first and secondterminals exposed through said protective layer of polymer.
 50. Thesystem of claim 49 further comprising a solder bump, solder ball, orwire bond pad connected to said first and second terminals.
 51. Thesystem of claim 46 wherein said capacitor has top and bottom plates, anda dielectric layer between said top and bottom plates.
 52. The system ofclaim 51, wherein said dielectric layer is Si₃N₄, TEOS, Ta₂O₅, TiO₂,SrTiO₃, or SiON.
 53. The system of claim 51, wherein said dielectriclayer is a polymer, and wherein said polymer is polyimide,benzocyclobutene (BCB), parylene or an epoxy-based material.
 54. A postpassivation system, comprising: a semiconductor substrate, having atleast one interconnect metal layer over said semiconductor substrate,and a passivation layer over the at least one interconnect metal layer,wherein the passivation layer comprises at least one passivation openingthrough which is exposed at least one top level metal contact point; apassive device, formed over said passivation layer; metalinterconnections, formed of a different material than said passivedevice and formed over said passivation layer, and connected to at leastone of said top level metal contact points; wherein said passivationopening's width is larger than about 0.1 um.
 55. The system of claim 54wherein said passive device is a resistor.
 56. The system of claim 54further comprising a protective layer of polymer formed over saidresistor and over said passivation layer.
 57. The system of claim 55wherein said resistor has first and second terminals, said first andsecond terminals exposed through said protective layer of polymer. 58.The system of claim 57 further comprising a solder bump, solder ball, orwire bond pad connected to said first and second terminals.
 59. A methodof forming a post passivation system, comprising: providing asemiconductor substrate, having at least one interconnect metal layerover said semiconductor substrate, and a passivation layer over the atleast one interconnect metal layer, wherein the passivation layercomprises at least one passivation opening through which is exposed atleast one top level metal contact point; and forming a passive device,formed over said passivation layer and connected to said at least onetop level metal contact point; wherein said at least one passivationopening is formed to a width larger than about 0.1 um.
 60. The method ofclaim 59 further comprising forming a polymer layer over saidpassivation layer and under said passive device.
 61. The method of claim60 wherein said polymer layer has at least one polymer opening, whereinsaid polymer opening is aligned with said passivation opening.
 62. Themethod of claim 61 wherein said polymer opening is formed larger thansaid passivation opening.
 63. The method of claim 60, wherein saidpassive device is connected to one or more of said top level metalcontact points through said polymer opening and said passivationopening.
 64. The method of claim 61, wherein metal used to form saidpassive device and to connect said passive device to said one or more ofsaid top level metal contact points is formed to completely coversidewalls of said polymer opening.
 65. The method of claim 63, whereinmetal used to form said passive device and to connect said passivedevice to said one or more of said top level metal contact points isformed to only partially cover sidewalls of said polymer opening. 66.The method of claim 60 wherein said polymer layer comprises polyimide,benzocyclobutene (BCB), parylene or an epoxy-based material.
 67. Themethod of claim 60 wherein said polymer layer is deposited by spincoating.
 68. The method of claim 60 wherein said polymer layer isdeposited by screen printing.
 69. The method of claim 60 wherein saidpolymer layer is deposited by laminating a dry film of said polymer. 70.The method of claim 59 wherein said passive device is a capacitor. 71.The method of claim 70 further comprising forming metalinterconnections, of a same material as said capacitor and formed oversaid passivation layer, and connected to at least one of said top levelmetal contact points.
 72. The method of claim 71 wherein said metalinterconnections and said capacitor are formed by: forming a polymerlayer over said passivation layer; and forming at least one polymeropening in said polymer layer, wherein said polymer opening is alignedwith said passivation opening, wherein said at least one polymer openingis formed larger than said passivation opening.
 73. The method of claim72 further comprising the steps of: forming a glue/barrier layer in saidat least one passivation opening, in said at least one polymer opening,and over said polymer layer; forming a seed layer over said bottomglue/barrier layer; and forming a bulk layer over said seed layer. 74.The method of claim 73 wherein said bottom glue/barrier layer is TiW,said seed layer is Au, and said bulk layer is Au.
 75. The method ofclaim 74, wherein said bottom glue/barrier of TiW is formed bysputtering, to a thickness of between about 500 and 5000 Angstroms. 76.The method of claim 74, wherein said seed layer of Au is formed bysputtering, to a thickness of between about 300 and 3000 Angstroms. 77.The method of claim 74, wherein said bulk layer of Au is formed byelectroplating, to a thickness of between about 1 and 20 um.
 78. Themethod of claim 73 wherein said bottom glue/barrier layer is Cr or Ti,said seed layer is Cu, and said bulk layer is Cu.
 79. The method ofclaim 78, wherein said bottom glue/barrier of Cr or Ti is formed bysputtering, to a thickness of between about 200 and 1500 Angstroms 80.The method of claim 78, wherein said seed layer of Cu is formed bysputtering, to a thickness of between about 2000 and 10000 Angstroms.81. The method of claim 78, wherein said bulk layer of Cu is formed byelectroplating, to a thickness of between about 2 and 20 μm.
 82. Themethod of claim 78 further comprising forming a cap layer of Ni formedover said bulk layer of Cu.
 83. The method of claim 82 wherein said caplayer of Ni is formed to a thickness of between about 0.1 and 3 um. 84.The method of claim 59 wherein said passive device has first and secondterminals, said first and second terminals each being connected downwardto one of said top level metal contact points.
 85. The method of claim59 further comprising forming a protective layer of polymer over saidpassive device and over said passivation layer.
 86. The method of claim85 wherein said passive device has first and second terminals, saidfirst terminal being connected to one of said top level metal contactpoints, and said second terminal exposed through said protective layerof polymer.
 87. The method of claim 86 further comprising forming asolder bump, solder ball, or wire bond pad connected to said secondterminal.
 88. The method of claim 70, wherein said capacitor is formedof bottom and top plates, with a dielectric layer between said bottomand top plates.
 89. The method of claim 88, wherein said dielectriclayer is formed of Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON.
 90. Thesystem of claim 88, wherein said dielectric layer is a polymer, andwherein said polymer is polyimide, benzocyclobutene (BCB), parylene oran epoxy-based material.
 91. The method of claim 88 further comprisingforming a first polymer layer formed over said passivation layer andunder said capacitor.
 92. The method of claim 90 wherein said firstpolymer layer has at least one first polymer opening, wherein said firstpolymer opening is aligned with said passivation opening.
 93. The methodof claim 91 wherein said first polymer opening is larger than saidpassivation opening.
 94. The method of claim 92 wherein said firstpolymer opening is smaller than said passivation opening.
 95. The methodof claim 93 wherein said dielectric layer has a dielectric layer openingaligning with said passivation opening, wherein said dielectric layeropening is larger than said first polymer opening.
 96. The method ofclaim 94 wherein said dielectric layer has a dielectric layer openingaligning with said passivation opening, wherein said dielectric layeropening is smaller than said first polymer opening.
 97. The method ofclaim 59 wherein said passive device is a resistor.
 98. The method ofclaim 97 further comprising forming metal interconnections, of adifferent material from said resistor, formed over said passivationlayer, and connected to at least one of said top level metal contactpoints.
 99. The method of claim 98 wherein said metal interconnectionsare formed by: forming a polymer layer over said passivation layer; andforming at least one polymer opening in said polymer layer, wherein saidpolymer opening is aligned with said passivation opening, wherein saidat least one polymer opening is formed larger than said passivationopening.
 100. The method of claim 99 further comprising the steps of:forming a glue/barrier layer in said at least one passivation opening,in said at least one polymer opening, and over said polymer layer;forming a seed layer over said bottom glue/barrier layer; and forming abulk layer over said seed layer.
 101. The method of claim 100 whereinsaid bottom glue/barrier layer is TiW, said seed layer is Au, and saidbulk layer is Au.
 102. The method of claim 101, wherein said bottomglue/barrier of TiW is formed by sputtering, to a thickness of betweenabout 500 and 5000 Angstroms.
 103. The method of claim 101, wherein saidseed layer of Au is formed by sputtering, to a thickness of betweenabout 300 and 3000 Angstroms.
 104. The method of claim 101, wherein saidbulk layer of Au is formed by electroplating, to a thickness of betweenabout 1 and 20 um.
 105. The method of claim 100 wherein said bottomglue/barrier layer is Cr or Ti, said seed layer is Cu, and said bulklayer is Cu.
 106. The method of claim 105, wherein said bottomglue/barrier of Cr or Ti is formed by sputtering, to a thickness ofbetween about 200 and 1500 Angstroms.
 107. The method of claim 105,wherein said seed layer of Cu is formed by sputtering, to a thickness ofbetween about 2000 and 10000 Angstroms.
 108. The method of claim 105,wherein said bulk layer of Cu is formed by electroplating, to athickness of between about 2 and 20 μm.
 109. The method of claim 105further comprising forming a cap layer of Ni formed over said bulk layerof Cu.
 110. The method of claim 109 wherein said cap layer of Ni isformed to a thickness of between about 0.1 and 3 um.
 111. The method ofclaim 97 wherein said resistor has first and second terminals, saidfirst and second terminals each being connected downward to one of saidtop level metal contact points.
 112. The method of claim 97 furthercomprising forming a protective layer of polymer over said resistor andover said passivation layer.
 113. The method of claim 112 wherein saidresistor has first and second terminals, said first terminal beingconnected to one of said top level metal contact points, and said secondterminal exposed through said protective layer of polymer.
 114. Themethod of claim 113 further comprising forming a solder bump, solderball, or wire bond pad connected to said second terminal.
 115. Themethod of claim 97, wherein said resistor is formed of TaN, NiCr, NiSn,tungsten (W), TiW, TiN, Cr, Ti, TaSi or Ni.
 116. A method of forming apost passivation system, comprising: providing a semiconductorsubstrate, having at least one interconnect metal layer over saidsemiconductor substrate, and a passivation layer over the at least oneinterconnect metal layer, wherein the passivation layer comprises atleast one passivation opening through which is exposed at least one toplevel metal contact point; forming a passive device over saidpassivation layer; forming metal interconnections, formed of a samematerial as said passive device and formed over said passivation layer,and connected to at least one of said top level metal contact points;wherein said passivation opening's width is larger than about 0.1 um.117. The method of claim 116 wherein said passive device is a capacitor.118. The method of claim 117 further comprising forming a protectivelayer of polymer formed over said capacitor and over said passivationlayer.
 119. The method of claim 118 wherein said capacitor has first andsecond terminals, said first and second terminals exposed through saidprotective layer of polymer.
 120. The system of claim 119, wherein saidcapacitor has bottom and top plates, with a dielectric layer betweensaid bottom and top plates, wherein one of said first and secondterminals connected to one of said bottom and top plates, and whereinanother of said first and second terminals is connected to another ofsaid bottom and top plates.
 121. The method of claim 119 furthercomprising a solder bump, solder ball, or wire bond pad connected tosaid first and second terminals.
 122. The method of claim 116 whereinsaid capacitor has top and bottom plates, and a dielectric layer betweensaid top and bottom plates.
 123. A method of forming a post passivationsystem, comprising: providing a semiconductor substrate, having at leastone interconnect metal layer over said semiconductor substrate, and apassivation layer over the at least one interconnect metal layer,wherein the passivation layer comprises at least one passivation openingthrough which is exposed at least one top level metal contact point;forming a resistor over said passivation layer; forming metalinterconnections, formed of a different material as said resistor andformed over said passivation layer, and connected to at least one ofsaid top level metal contact points; wherein said passivation opening'swidth is larger than about 0.1 um.
 124. The method of claim 123 furthercomprising forming a protective layer of polymer formed over saidresistor and over said passivation layer.
 125. The method of claim 124wherein said resistor has first and second terminals, said first andsecond terminals exposed through said protective layer of polymer. 126.The method of claim 125 further comprising a solder bump, solder ball,or wire bond pad connected to said first and second terminals.
 127. Themethod of claim 59, wherein said polymer layer is formed only underpassive device, to form polymer islands, thereby reducing stress in saidpolymer layer.